PhD’s Thesis [2022] – TBD
Work in progress…
Documents: text,
slides
GitHub Code: TBD
Master’s Thesis [2019] – Benchmarking Data Stream Processing Frameworks on Multicores
The work shows a comparison in terms of performance between traditional Data Stream Processing (DaSP) systems and WindFlow, an efficient C++17 streaming library based on FastFlow’s building blocks. The goal is to quantify the benefit that may be achieved by using the C++ solution with respect to modern Java-based ones. A benchmark of four real-world DaSP applications have been designed and implementations are provided using Apache Storm, Apache Flink and WindFlow. Experiments show a significant throughput improvement and latency reduction by using the C++ solution with respect to the state-of-the-art frameworks on single multicore machines. The results obtained are encouraging for future works which aim at designing innovative DaSP frameworks based on C++ and providing high-level abstractions like Storm and Flink, that may be able to overcome modern Java-based Stream Processing Engines (SPEs) on distributed scenarios too. The entire work has been supervised by Dr. Gabriele Mencagli and contributes to the WindFlow project. The thesis document and the presentation are available in English at the following links. The developed code is open source and entirely accessible on GitHub (links below).
Documents: text,
slides
GitHub Code:
Storm ,
Flink ,
WindFlow
Bachelor’s Thesis [2016] – Programming Techniques for FPGA Devices
The work has been supervised by Prof. Marco Danelutto and is a dissertation about FPGA (Field Programmable Gate Array) programming methodologies (Hardware Description Languages, Chisel and OpenCL), with an overview of current technological trends. Programming methologies offering a higher lever of abstraction with respect to the underlying hardware improve the usability aspect and extend the range of programmers which are able to access the technology. However, highering the abstraction level reflects in general in performance results that are worse with respect to the ones obtained by using a HDL approach. In order to design a good (in terms of performance) Verilog or VHDL program, an expert HDL programmer is needed, who is required to know all the architecture’s details and must be able to exploit at best the low level constructs offered by the HDL in order to write well optimized code. Chisel is an example of high-level HDL which adds hardware construction primitives to the Scala programming language. The idea is to simplify the design of a parameterizable circuit by exploiting a modern programming language such as Scala and at the same time preserving the performance aspect by producing synthesizable Verilog code, generated from the Chisel modules. The OpenCL standard allows for the implementation of parallel algorithms that can guarantee portability among different platforms (CPUs, GPUs, FPGAs) with minimal recoding and inherently offers the ability of expressing parallel algorithms to be implemented on FPGAs at a much higher level of abstraction than HDLs. In fact, the OpenCL language is based on C programming language, enriched with extensions that allow for the specification of parallelism. Hence, the general trend is to reach optimal performance, or at least comparable to the one achievable by using low-level HDL approaches, and at the same time try to increase the abstraction level in order to expand the range of programmers that are able to access the FPGA technology. The thesis document and the presentation (links below) are both in Italian language.